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NCP5387 2/3/4 Phase Controller for CPU Applications
The NCP5387 is a two-, three-, or four-phase buck controller which combines differential voltage and current sensing, and adaptive voltage positioning to power both AMD and Intel processors. Dual-edge pulse-width modulation (PWM) combined with inductor current sensing reduces system cost by providing the fastest initial response to transient load events. Dual-edge multi-phase modulation reduces total bulk and ceramic output capacitance required to satisfy transient load-line regulation. A high performance operational error amplifier is provided, which allows easy compensation of the system. The proprietary method of Dynamic Reference Injection (Patented) makes the error amplifier compensation virtually independent of the system response to VID changes, eliminating tradeoffs between overshoot and dynamic VID performance.
Features http://onsemi.com MARKING DIAGRAM
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1 40 40 PIN QFN, 6x6 MN SUFFIX CASE 488AR NCP5387 AAWLYYWW G
* * * * * * * * * * * * * * * * * *
Meets Intel's VR 10.0 and 11.0 and AMD Specifications Dual-Edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifier Supports both VR11 and Legacy Soft-Start Modes Dynamic Reference Injection (Patented) DAC Range from 0.5 V to 1.6 V "0.5% System Voltage Accuracy from 1.0 V to 1.6 V True Differential Remote Voltage Sensing Amplifier Phase-to-Phase Current Balancing "Lossless" Differential Inductor Current Sensing Differential Current Sense Amplifiers for each Phase Adaptive Voltage Positioning (AVP) Frequency Range: 100 kHz - 1.0 MHz OVP with Resettable, 8 Event Delayed Latch Threshold Sensitive Enable Pin for VTT Sensing Power Good Output with Internal Delays Programmable Soft-Start Time This is a Pb-Free Device*
NCP5387 = Specific Device Code AA = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G/G = Pb-Free Package *Pin 41 is the thermal pad on the bottom of the device.
ORDERING INFORMATION
Device NCP5387MNR2G* Package Shipping
QFN-40 2500 / Tape & Reel (Pb-Free)
*Temperature Range: 0C to 85C For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Applications
* Desktop Processors
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2007
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April, 2007 - Rev. 3
Publication Order Number: NCP5387/D
NCP5387
PIN CONNECTIONS
40 39 38 37 36 35 34 33 32 G3 31 G2
VR_HOT
NTC
VR_FAN
VCC
VR_RDY
1 2 3 4 5 6 7 8 9 10
12VMON
VREF
G4
EN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7
G1 DRVON CS4 CS4N
30 29 28 27 26 25 24 23 22 21
NCP5387
CS3 CS3N CS2 CS2N CS1 DIFFOUT COMP
ROSC
DACMODE SS
11
12
13
14
15
16
17
18
19
(Top View)
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20
VDRP
CS1N
ILIM
VFB
VS+
VS-
NC
NCP5387
+5 V VTT 680 W PULLUPS RVCC CVCC1 NCP3418B 41 36 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_HOT VR_FAN 2 3 4 5 6 7 8 9 10 1 37 40 39 16 15 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VR10/11 EN VR_RDY VR_HOT VR_FAN VS- VS+ G3 G2 31 VREF NTC GND 12VMON 35 34 38 RNTC1 C1 NTD85N02RT4 CS1 RNTC2 2 RT1 3 OD IN 4 VCC BST DRVH SW DRVL PGND 1 8 7 5 6 R2 RS1 C2 NTD60N02RT4 L1 12 V_FILTER D1 BAT54HT1 C3 12 V_FILTER C4
30 G1 22 CS1 CS1N 21 12 V_FILTER 12 V_FILTER
24 CS2 CS2N 23 32 4 3 VCC OD IN BST DRVH SW DRVL 2 PGND 1 8 7 5 6
RISO1 RT2
RISO2
NCP5387
26 CS3 CS3N 25 33
CFB1 RFB
RFB1 17 19 RDRP 20 VDRP DRVON DIFFOUT VFB G4
28 CS4 CS4N 27 12 V_FILTER 29 12 V_FILTER
CD1
RD1 18 COMP ILIM 13 CH RLIM1 CSS 2 IN ROSC SS 12 11 3 4 VCC OD BST DRVH SW DRVL PGND 1 8 7 5 6
CF
RF
RVFB
RLIM2
12 V_FILTER
12 V_FILTER
4 3 2
VCC OD IN
BST DRVH SW DRVL PGND
1 8 7 5 6
RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU GND
Figure 1. Application Schematic for Four Phases http://onsemi.com
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NCP5387
+5 V VTT 680 W PULLUPS RVCC CVCC1 NCP3418B 41 36 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_HOT VR_FAN 2 3 4 5 6 7 8 9 10 1 37 40 39 16 15 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VR10/11 EN VR_RDY VR_HOT VR_FAN VS- VS+ G3 G2 31 VREF NTC 12VMON 35 34 RNTC1 38 RNTC2 2 IN GND RT1 4 3 VCC OD BST DRVH SW DRVL PGND 1 8 7 5 6 R2 RS1 NTD85N02RT4 C2 CS1 NTD60N02RT4 L1 12 V_FILTER D1 BAT54HT1 C4 C3 12 V_FILTER
C1
30 G1 22 CS1 CS1N 21 12 V_FILTER 12 V_FILTER
24 CS2 CS2N 23 32 4 3 VCC OD IN BST DRVH SW DRVL 2 PGND 1 8 7 5 6
RISO1
RT2
RISO2
NCP5387
26 CS3 CS3N 25 33
CFB1 RFB
RFB1 17 19 RDRP 20 VDRP DRVON DIFFOUT VFB G4
28 CS4 CS4N 27 12 V_FILTER 29 12 V_FILTER
CD1
RD1 18 COMP ILIM 13 CH RLIM1 ROSC SS 12 11 3 CSS 2 IN 4 VCC OD BST DRVH SW DRVL PGND 1 8 7 5 6
CF
RF
RVFB
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS
VCCP + VSSP CPU GND
Figure 2. Application Schematic for Three Phases
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NCP5387
+5 V VTT 680 W PULLUPS RVCC CVCC1 NCP3418B 41 36 VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_HOT VR_FAN 2 3 4 5 6 7 8 9 10 1 37 40 39 16 15 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VR10/11 EN VR_RDY VR_HOT VR_FAN VS- VS+ G3 G2 31 VREF NTC 12VMON 35 34 38 RNTC1 C1 NTD85N02RT4 GND RNTC2 2 RT1 4 3 VCC OD IN BST DRVH SW DRVL PGND 1 8 7 5 6 R2 RS1 C2 CS1 NTD60N02RT4 L1 12 V_FILTER D1 BAT54HT1 C3 12 V_FILTER C4
30 G1 22 CS1 CS1N 21 12 V_FILTER 12 V_FILTER
24 CS2 CS2N 23 32 4 3 VCC OD IN BST DRVH SW DRVL 2 PGND 1 8 7 5 6
RISO1
RT2
RISO2
NCP5387
26 CS3 CS3N 25 33
CFB1 RFB
RFB1 17 19 DIFFOUT VFB
G4
28 CS4 CS4N 27
RDRP 20 CD1 RD1 18 CF RF COMP ILIM 13 CH RVFB RLIM1 CSS ROSC SS 12 11 VDRP DRVON 29
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU GND
Figure 3. Application Schematic for Two Phases
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NCP5387
VREF DACMODE VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 SS
NTC NCP5387 VR10/11/AMD DAC + - DAC + VR_HOT VR_FAN NTC
VS- VS+ DIFFOUT
- + Diff Amp Fault 1.3 V + - Error Amp
-
VFB
GND
COMP VDRP Droop Amplifier
+-
1.3 V CS1 CS1N CS2 CS2N CS3 CS3N CS4 CS4N + -
Gain = 6
+ - + - + - + -
4OFF OVER Fault
ENB
G1
+ -
Gain = 6
ENB
G2
+ -
Gain = 6
ENB
G3
+ -
Gain = 6
ENB
G4
Oscillator ROSC DIFFOUT
+ ILIM EN VCC - + - VCC UVLO 12VMON + - 12VMON UVLO ILimit
Fault Logic 3 Phase Detect and Monitor Circuits
DRVON
VR_RDY
Figure 4. Simplified Block Diagram http://onsemi.com
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NCP5387
PIN DESCRIPTIONS
Pin No. 1 Symbol EN Description Pull this pin high to enable controller. Pull this pin low to disable controller. Either an open-collector output (with a pull-up resistor) or a logic gate (CMOS or totem-pole output) may be used to drive this pin. A Low-to-High transition on this pin will initiate a soft start. Connect this pin directly to VREF if the Enable function is not required. 20 MHz filtering at this pin is required. Voltage ID DAC inputs VRM select bit A capacitor from this pin to ground programs the soft-start time. A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies an output voltage of 2 V which may be used to form a voltage divider to the ILIM pin to set the over-current shutdown threshold as shown in the Applications Schematics. Over-current shutdown threshold. To program the shutdown threshold, connect this pin to the ROSC pin via a resistor divider as shown in the Applications Schematics. To disable the over-current feature, connect this pin directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin; do not connect this pin to any externally generated voltages. Do not connect anything to this pin. Non-inverting input to the internal differential remote sense amplifier Inverting input to the internal differential remote sense amplifier Output of the differential remote sense amplifier Output of the error amplifier, and the non-inverting input of the PWM comparators Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and the amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP) during load. Current signal output for Adaptive Voltage Positioning (AVP). The voltage of this pin above the 1.3 V internal offset voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP current into the feedback resistor (RFB) to produce an output voltage droop. Leave this pin open for no AVP. Inverting input to current sense amplifier #x, x = 1, 2, 3, 4. Non-inverting input to current sense amplifier #x, x = 1, 2, 3, 4. Output to enable Gate Drivers PWM output pulses to gate drivers Voltage reference output. This pin is used for remote temperature sensing as shown in the Applications Schematic. Second UVLO monitor for monitoring the power stage supply rail Power for the internal control circuits. Voltage Regulator Ready (Power Good) output. Open drain output that is high when the output is regulating. Remote temperature sense connection. Connect an NTC thermistor from this pin to GND and a resistor from this pin to VREF. As the NTC's temperature increases, the voltage on this pin will decrease. Open drain output that will be low impedance when the voltage at the NTC pin is above the specified threshold. This pin will transition to a high impedance state when the voltage at the NTC pin decreases below the specified threshold. This pin requires an external pull-up resistor. Open drain output that will be low impedance when the voltage at the NTC pin is above the specified threshold. This pin will transition to a high impedance state when the voltage at the NTC pin decreases below the specified threshold. This pin requires an external pull-up resistor. Power supply return (QFN Flag)
2-9 10 11 12
VID0-VID7 DACMODE SS ROSC
13
ILIM
14 15 16 17 18 19
NC VS+ VS- DIFFOUT COMP VFB
20
VDRP
21, 23, 25, 27 22, 24, 26, 28 29 30 - 33 34 35 36 37 38 39
CSxN CSx DRVON G1 - G4 VREF 12VMON VCC VR_RDY NTC VR_FAN
40
VR_HOT
41
GND
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NCP5387
MAXIMUM RATINGS Electrical Information
Pin Symbol COMP VDRP VS+ VS- DIFFOUT VR_RDY, VR_HOT, VR_FAN VCC ROSC DACMODE, EN VREF All Other Pins *All signals reference to GND unless otherwise noted. VMAX (V) 5.5 5.5 2.0 2.0 5.5 5.5 7.0 5.5 3.5 5.5 5.5 VMIN (V) -0.3 -0.3 GND - 300 mV GND - 300 mV -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 ISOURCE (mA) 10 5 1 1 20 N/A N/A 1 0 0.5 - ISINK (mA) 10 5 1 1 20 20 10 N/A 0 N/A -
Thermal Information
Rating Thermal Characteristic, QFN Package (Note 1) Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level, QFN Package Symbol RqJA TJ TA TSTG MSL Value 34 0 to 125 0 to 85 -55 to +150 3 Unit C/W C C C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 Airflow. 2. JESD 51-7 (1S2P Direct-Attach Method) with 0 Airflow.
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
Error Amplifier
Input Bias Current Input Offset Voltage (Note 3) Open Loop DC Gain (Note 3) Open Loop Unity Gain Bandwidth (Note 3) Open Loop Phase Margin (Note 3) Slew Rate (Note 3) CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND DVin = 100 mV, G = -10 V/V, 1.5 V < COMP < 2.5 V, CL = 60 pF, DC Load = 125 mA 10 mV of Overdrive ISOURCE = 2.0 mA 10 mV of Overdrive ISINK = 2.0 mA 10 mV Input Overdrive COMP = 2.0 V 10 mV Input Overdrive COMP = 1.0 V -200 -1.0 - - - - - - 100 15 70 5 200 1.0 - - - - nA mV dB MHz V/ms
Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3)
2.20 - 2.0 2.0
VCC-20 mV 0.01 - -
- 0.5 - -
V V mA mA
Differential Summing Amplifier
VS+ Input Resistance VS+ Input Bias Voltage VS- Bias Current VS+ Input Voltage Range VS- Input Voltage Range DC Gain VS+ to DIFFOUT DAC Accuracy (measured at VS+) DRVON = Low DRVON = High DRVON = Low DRVON = High VS- = 0 V 0.95 v DDIFFOUT / DVS- v 1.05 0.5 V v DIFFOUT v 2.0 V 0.95 v DDIFFOUT / DVS- v 1.05 0.5 V v DIFFOUT v 2.0 V 0 V v DAC - VS+ v 0.3 V Closed loop measurement including error amplifier. (See Figure 25) 1.0 v DAC v 1.6 0.8 v DAC v 1.0 0.5 v DAC v 0.8 CL = 80 pF to GND, RL = 10 kW to GND DVin = 100 mV, DIFFOUT = 1.3 V to 1.2 V VS+ - DAC = 1.0 V ISOURCE = 2.0 mA VS+ - DAC = -0.8 V ISINK = 2.0 mA VS+ - DAC = 1.0 V DIFFOUT = 1.0 V VS+ - DAC = -0.8 V DIFFOUT = 1.0 V - - - - - -0.3 -0.3 0.98 1.5 17 0.05 0.65 33 - - 1.0 - - - - - 2.0 0.3 1.025 kW V mA V V V/V
-0.5 -5 -8 - - 2.0 - 2.0 2.0
- - - 10 5 3.0 0.01 - -
0.5 5 8 - - - 0.5 - -
% mV mV MHz V/ms V V mA mA
-3dB Bandwidth (Note 3) Slew Rate (Note 3) Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3)
3. Guaranteed by design. Not tested in production.
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
Internal Offset Voltage
VDRP pin offset voltage AND Error Amp input voltage - 1.30 V
VDRP Adaptive Voltage-Positioning Amplifier
Current Sense Input to VDRP Gain Current Sense Input to VDRP -3dB Bandwidth (Note 3) VDRP Output Slew Rate (Note 3) -60 mV < (CSx-CSxN) < +60 mV (Each CS Input Independently) CL = 30 pF to GND, RL = 10 kW to GND DVin = 25 mV 1.3 V < VDRP < 1.9 V, CL = 330 pF to GND, RL = 1 kW to 10 kW connected to 1.3 V CSx= CSxN = 1.3 V CSx - CSxN = 0.1 V (all phases), ISOURCE = 1.0 mA CSx - CSxN = -0.033 V (all phases), ISINK = 1.0 mA VDRP = 2.0 V VDRP = 1.0 V 5.64 - 2.5 5.79 4 - 5.95 - - V/V MHz V/ms
VDRP Output Voltage Offset from Internal Offset Voltage Maximum VDRP Output Voltage Minimum VDRP Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3)
-15 2.6 - - -
- 3.0 0.1 1.3 25
+15 - 0.5 - -
mV V V mA mA
Current Sense Amplifiers
Input Bias Current Common Mode Input Voltage Range Differential Mode Input Voltage Range (Note 3) Input Referred Offset Voltage (Note 3) Current Sense Input to PWM Gain CSx = CSxN = 1.0 V 0 V < (CSx - CSxN) < 0.1 V CSx = CSxN = 1.4 V -200 -0.3 -120 -1.0 - - - - - 6.0 200 2.0 120 1.0 - nA V mV mV V/V
Oscillator
Switching Frequency Range (Note 3) Switching Frequency Accuracy, 2- or 4-phase Switching Frequency Accuracy, 3-phase Switching Frequency Tolerance, 2 and 4 Phase Operation (Note 3) Switching Frequency Tolerance, 3 Phase Operation (Note 3) ROSC Output Voltage ROSC = 50 kW 25 kW 10 kW 50 kW 25 kW 10 kW 100 196 380 803 196 370 757 - - - - 1.95 - - - - - - - 5 10 10 15 2.01 1000 226 420 981 230 430 963 - - - - 2.065 kHz kHz
ROSC =
kHz
200 kHz < FSW < 600 kHz 100 kHz < FSW <1 MHz 200 kHz < FSW < 600 kHz 100 kHz < FSW <1 MHz 40 mA IROSC 200 mA
% % V
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
Modulators (PWM Comparators)
Minimum Pulse Width (Note 3) Propagation Delay (Note 3) Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle PWM Linear Duty Cycle (Note 3) PWM Phase Angle Error COMP voltage when the PWM outputs remain LOW COMP voltage when the PWM outputs remain HIGH Fs = 800 kHz - - - - - - -15 30 20 1.0 1.3 2.3 90 - 40 - - - - - 15 ns ns V V V %
VR_RDY (Power Good) Output
VR_RDY Saturation Voltage VR_RDY Rise Time IVR_RDY = 10 mA External pullup of 680 kW to 1.25 V, CL = 45 pF, DVo = 10% to 90% VR_RDY = 5.0 V VCORE increasing, DAC = 1.3 V - - - - 0.4 150 V ns
VR_RDY High - Output Leakage Current VR_RDY Upper Threshold Voltage
- -
- 300
1.0 -
mA mV below DAC mV below DAC ms ns
VR_RDY Lower Threshold Voltage
VCORE decreasing, DAC = 1.3 V
-
350
-
VR_RDY Rising Delay VR_RDY Falling Delay
VCORE increasing VCORE decreasing
- -
- -
3 250
PWM Outputs
Output High Voltage Output Low Voltage Rise Time Fall Time Tri-State Output Leakage Output Impedance - Sourcing Output Impedance - Sinking Sourcing 500 mA Sinking 500 mA CL = 20 pF, DVo = 0.3 to 2.0 V CL = 20 pF, DVo = Vmax to 0.7 V Gx = 2.5 V, x = 1 - 4 Max Resistance to VCC Max Resistance to GND 3.0 - - - - - - - - - - - 320 140 VCC 0.15 20 20 1.5 - - V V ns ns mA W W
2/3/4 Phase Detection
Gate Pin Source Current Gate Pin Threshold Voltage Phase Detect Timer - - - 84 225 20 - - - mA mV ms
DRVON
Output High Voltage Output Low Voltage Rise Time Fall Time Internal Pulldown Resistance Sourcing 500 mA Sinking 500 mA CL (PCB) = 20 pF, DVo = 10% to 90% CL = 20 pF, DVo = 10% to 90% 3.0 - - - - - - 24 11 70 VCC 0.7 30 20 - V mV ns ns kW
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
Soft-Start
Soft-Start Pin Source Current Soft-Start Ramp Time Soft-Start Pin Discharge Voltage VR11 Dwell Time at VBOOT CSS = 0.01 mF; Time to 1.05 V DRVON pin = LO (Fault) CSS = 0.01 mF 3.75 - - 50 5.0 2.2 - - 6.25 - 25 500 mA ms mV ms
DACMODE Input
Input Range for AMD Operating Mode Input Range for VR11 Operating Mode Input Range for VR10 Operating Mode 2.3 0.9 0 - - - 3.5 1.7 0.5 V V V
Enable Input
Enable High Input Leakage Current Rising Threshold Falling Threshold Hysteresis Enable Delay Time Disable Delay Time EN = 3.3 V VUPPER VLOWER VUPPER - VLOWER Time from Enable transitioning HI to initiation of Soft-Start EN Low to DRVON Low - 0.800 0.670 - 1.0 - - - - 130 - 150 1.0 0.920 0.830 - 5.0 200 mA V V mV ms ns
Current Limit
Current Sense Amp to ILIM Gain ILIM Pin Input Bias Current ILIM Pin Working Voltage Range (Note 3) ILIM Offset Voltage Delay (Note 3) Offset extrapolated to CSx - CSxN = 0, referred to ILIM pin 20 mV < (CSx - CSxN) < 60 mV (Each CS Input Independently) VILIM = 2.0 V 5.7 - 0.2 -33 - 5.95 - - 17 300 6.2 1.0 2.0 67 - V/V mA V mV ns
Overvoltage Protection
Overvoltage Threshold Delay (Note 3) DAC+ 160 - - 100 DAC+ 200 - mV ns
Undervoltage Protection
VCC UVLO Start Threshold VCC UVLO Stop Threshold VCC UVLO Hysteresis 4 3.8 100 - - 215 4.5 4.3 - V V mV
VID Inputs
Upper Threshold Lower Threshold Input Bias Current Delay before Latching VID Change (VID De-Skewing) (Note 3) Measured from the edge of the first VID change VUPPER VLOWER - 300 - 500 - - - - 800 - 500 800 mV mV nA ns
Internal DAC Slew Rate Limiter
Positive Slew Rate Limit Negative Slew Rate Limit VID Step of +500 mV VID Step of -500 mV - - 6.3 -6.3 - - mV/ms mV/ms
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
Voltage Reference (VREF)
VREF Output Voltage 0 mA v IVREF v 500 mA 2.469 2.52 2.569 V
Input Supply Current
VCC Operating Current EN = LOW, No PWM - - 20 mA
Temperature Sensing
VR_FAN Upper Voltage Threshold VR_FAN Lower Voltage Threshold VR_HOT Upper Voltage Threshold VR_HOT Lower Voltage Threshold VR_FAN Output Saturation Voltage VR_FAN Output Leakage Current VR_HOT Saturation Output Voltage VR_HOT Output Leakage Current NTC Pin Bias Current Fraction of VREF voltage above which VR_FAN output pulls low Fraction of VREF voltage below which VR_FAN output is open Fraction of VREF voltage above which VR_HOT output pulls low Fraction of VREF voltage below which VR_HOT output is open ISINK = 4 mA High Impedance State ISINK = 4 mA High Impedance State - - - - - - - - - 0.4 x VREF 0.33 x VREF 0.33 x VREF 0.27 x VREF - - - - - - - - - 0.3 1 0.3 1 1 - - - - V mA V mA mA
12VMON
12VMON (Rising Threshold) 12VMON (Falling Threshold) Sufficient power stage supply voltage Insufficient power stage supply voltage 0.728 0.643 - - 0.821 0.725 V V
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
VRM11 DAC
System Voltage Accuracy 1.0 V < DAC < 1.6 V 0.8 V < DAC < 1.0 V 0.5 V < DAC < 0.8 V With CS Input DVin = 0 V - - 0.5 5 8 - % mV mV mV
No Load Offset Voltage from Nominal DAC Specification
-
-19
Table 1: VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Voltage (V) OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24
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NCP5387
Table 1: VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 VID3 50 mV 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID2 25 mV 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 12.5 mV 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Voltage (V) 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 HEX 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
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NCP5387
Table 1: VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 VID6 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID4 100 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 VID3 50 mV 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 VID2 25 mV 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 VID1 12.5 mV 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 VID0 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Voltage (V) 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 HEX 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80
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NCP5387
Table 1: VRM11 VID Codes
VID7 800 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID2 25 mV 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID1 12.5 mV 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Voltage (V) 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 HEX 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE
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NCP5387
Table 1: VRM11 VID Codes
VID7 800 mV 1 1 1 1 1 1 VID6 400 mV 0 0 0 0 1 1 VID5 200 mV 1 1 1 1 1 1 VID4 100 mV 0 1 1 1 1 1 VID3 50 mV 1 0 0 0 1 1 VID2 25 mV 1 0 0 0 1 1 VID1 12.5 mV 1 0 0 1 1 1 VID0 6.25 mV 1 0 1 0 0 1 Voltage (V) 0.51875 0.51250 0.50625 0.50000 OFF OFF OFF HEX AF B0 B1 B2 FE FF B3 to FD
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
VRM10 DAC
System Voltage Accuracy No Load Offset Voltage from Nominal DAC Specification 1.0 V < DAC < 1.6 V 0.83125 V < DAC < 1.0 V With CS Input DVin = 0 V - - - -19 0.5 5 - % mV mV
Table 2: VRM10 VID Codes
VID4 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID2 100 mV 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID1 50 mV 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID0 25 mV 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID5 12.5 mV 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID6 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875
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NCP5387
Table 2: VRM10 VID Codes
VID4 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID2 100 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID1 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 VID0 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 VID5 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID6 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal DAC Voltage (V) 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 OFF OFF OFF
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NCP5387
Table 2: VRM10 VID Codes
VID4 400 mV 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 200 mV 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 100 mV 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID1 50 mV 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID0 25 mV 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID5 12.5 mV 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) OFF 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125
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NCP5387
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Test Conditions Min Typ Max Units
AMD DAC
System Voltage Accuracy No Load Offset Voltage from Nominal DAC Specification 1.0 V < DAC < 1.55 V 0.8 V < DAC < 1.0 V With CS Input DVin = 0 V - - - 0 0.5 5.0 - % mV mV
Table 3: AMD VID Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal VOUT (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown Tolerance 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV -
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NCP5387
TYPICAL CHARACTERISTICS
2.526 VREF, REFERENCE VOLTAGE (V) VR_RDY DELAY TIME (ms) 10 20 30 40 50 60 70 1.60
2.524
1.58
1.56
2.522
1.54
2.520
1.52
2.518 0
1.50 80 90 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C) T, TEMPERATURE (C)
Figure 5. Voltage Reference (VREF) vs. Temperature
2.017 ISS, SOFT START CURRENT (mA) 4.90
Figure 6. VR Ready Delay Time vs. Temperature
2.016 ROSC VOLTAGE (V)
4.85
2.015
4.80
2.014
2.013 2.012 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C)
4.75
4.70 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C)
Figure 7. ROSC Voltage vs. Temperature
Figure 8. Soft Start Current vs. Temperature
10.5
REMOTE SENSE AMPLIFIER GAIN (V/V)
11.0 IS, SUPPLY CURRENT (mA)
1.003
1.002
DAC = 1.6 V DAC = 1.1 V
10.0
1.001 DAC = 0.5 V
9.5
9.0 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C)
1.000 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C)
Figure 9. Supply Current vs. Temperature
Figure 10. Remote Sense Amplifier Gain vs. Temperature
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NCP5387
TYPICAL CHARACTERISTICS
4.30 Start 12VMON THRESHOLD (V) UVLO THRESHOLD (V) 4.25 0.80 0.78 Start 0.76 0.74 0.72 0.70 0.68 0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C) T, TEMPERATURE (C)
4.20
4.15
4.10
Stop
Stop
4.05
Figure 11. UVLO Threshold vs. Temperature
Figure 12. 12VMON Threshold vs. Temperature
0.90 0.88 ENABLE THRESHOLD (V) RSA BIAS ERROR (mV) 0.86 0.84 0.82 0.80 0.78 0.76 0.74 0.72 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C) Stop Start
2.0
1.0 50C 0.0 25C -1.0 0C
85C
70C
Figure 13. Enable Threshold vs. Temperature
1.50 VDRP SOURCE CURRENT (mA) DAC SLEW RATE (mV/ms)
6.35 6.30
1.45
6.25 6.20 Rising 6.15 6.10 6.05 6.00
1.40
1.35
1.30 1.25 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C)
Figure 15. VDRP Source Current vs. Temperature
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2 12 22 32 42 52 62 72 82 92 102 112 122 132 142 152 162 172 182 DAC CODE
-2.0
Figure 14. Remote Sense Amplifier Bias Error vs. DAC Code
Falling
0
10
20
30
40
50
60
70
80
90
T, TEMPERATURE (C)
Figure 16. DAC Slew Rate vs. Temperature
NCP5387
TYPICAL CHARACTERISTICS
5.795 CS2 5.790 VDRP GAIN (V/V) 5.785 5.780 CS4 5.775 5.770 5.765 0 -1.0 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C) T, TEMPERATURE (C) CS1 CS3 VDRP OFFSET (mV) 2.0 3.0
1.0
0.0
Figure 17. VDRP Gain vs. Temperature
Figure 18. VDRP Offset vs. Temperature
0.3 FREQUENCY DEVIATION (%) 0.2 0.1 0.0 4ph 50k -0.1 -0.2 -0.3 0 10 20 30 40 50 60 T, TEMPERATURE (C) 4ph 25k 3ph 25k 3ph 50k 70 80 90 3ph 10k 4ph 10k THRESHOLD (mV)
360 350 340 330 320 310 300 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C) Upper
Lower
Figure 19. Switching Frequency Deviation vs. Temperature
3.0 Sinking DETECT CURRENT (mA) 2.0 DEVIATION (%) 77 78
Figure 20. VR_RDY Thresholds vs. Temperature
1.0
Sourcing
76
0.0
75
-1.0 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C)
74 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C)
Figure 21. PWM Output Resistance Deviation vs. Temperature
Figure 22. 2/3/4 Phase Detect Current vs. Temperature
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NCP5387
TYPICAL CHARACTERISTICS
20.5 DETECT THRESHOLD (mV) PHASE DETECT TIME (ms) 235 234 233 232 231 230 229 10 20 30 40 50 60 70 80 90 0 10 20 30 40 50 60 70 80 90 T, TEMPERATURE (C) T, TEMPERATURE (C)
20.4
20.3
20.2
20.1 0
Figure 23. Phase Detect Time vs. Temperature
Figure 24. 2/3/4 Phase Detect Threshold vs. Temperature
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NCP5387
FUNCTIONAL DESCRIPTION
General
The NCP5387 dual edge modulated multiphase PWM controller is specifically designed with the necessary features for a high current VR10, VR11 or AMD CPU power system. The IC consists of the following blocks: Precision Programmable DAC, Differential Remote Voltage Sense Amplifier, High Performance Voltage Error Amplifier, Differential Current Feedback Amplifiers, Precision Oscillator and Triangle Wave Generators, and PWM Comparators. Protection features include Undervoltage Lockout, Soft-Start, Overcurrent Protection, Overvoltage Protection, and Power Good Monitor.
Remote Output Sensing Amplifier (RSA)
Schematic. In 4-phase mode all 4 gate outputs are used as shown in the 4-phase Applications Schematic. The Current Sense inputs of unused channels should be connected to CSN of a channel that is used. The following truth table summarizes the modes of operation:
Gate Output Connections Mode 2-Phase 3-Phase 4-Phase G1 Normal Normal Normal G2 OPEN Normal Normal G3 Normal Normal Normal G4 OPEN GND Normal
These are the only allowable connection schemes to program the modes of operation.
Differential Current Sense Amplifiers
A true differential amplifier allows the NCP5387 to measure Vcore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VS+, and the Vcore ground reference point to VS-. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between Vcore and Vcore ground reference points. The RSA also subtracts the DAC (minus VID offset) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage to allow both positive and negative error voltages.
Precision Programmable DAC
A precision programmable DAC is provided. This DAC has 0.5% accuracy over the entire operating temperature range of the part. The DAC can be programmed to support either Intel VR10 or VR11 or AMD K8 specifications. A program selection pin is provided to accomplish this. This pin also sets the startup mode of operation. Connect this pin to 1.25 V to select the VR11 DAC table and startup mode. Connect this pin to ground to select the VR10 DAC table and the VR11 startup mode. Connect this pin to VREF to select the AMD DAC table and startup mode.
High Performance Voltage Error Amplifier
Four differential amplifiers are provided to sense the output current of each phase. The inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1, G2, G3, or G4). If a phase is unused, the differential inputs to that phase's current sense amplifier must be shorted together and connected to the output as shown in the 2- and 3-phase Application Schematics. A voltage is generated across the current sense element (such as an inductor or sense resistor) by the current flowing in that phase. The output of the current sense amplifiers are used to control three functions. First, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. In this function, all of the current sense outputs are summed so that the total output current is used for output voltage positioning. Second, the output signal is fed to the current limit circuit. This again is the summed current of all phases in operation. Finally, the individual phase current is connected to the PWM comparator. In this way current balance is accomplished.
Oscillator and Triangle Wave Generator
The error amplifier is designed to provide high slew rate and bandwidth. Although not required when operating as the controller of a voltage regulator, a capacitor from COMP to VFB is required for stable unity gain test configurations.
Gate Driver Outputs and 2/3/4 Phase Operation
The part can be configured to run in 2-, 3-, or 4-phase mode. In 2-phase mode, phases 1 and 3 should be used to drive the external gate drivers as shown in the 2-phase Applications Schematic. In 3-phase mode, gate output G4 must be grounded as shown in the 3-phase Applications
A programmable precision oscillator is provided. The oscillator 's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz/phase to 1.0 MHz/phase. The oscillator generates up to 4 triangle waveforms (symmetrical rising and falling slopes) between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2-, 3-, and 4-phase operation the PWM outputs are separated by 180, 120, and 90 angular degrees, respectively.
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NCP5387
PWM Comparators with Hysteresis
Four PWM comparators receive the error amplifier output signal at their noninverting input. Each comparator receives one of the triangle waves offset by 1.3 V at it's inverting input. The output of the comparator generates the PWM outputs G1, G2, G3, and G4. During steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by Vout/Vin. During a transient event, both high and low comparator output transitions shift phase to the points where the error amplifier output intersects the down and up ramp of the triangle wave. PROTECTION FEATURES
Undervoltage Lockout
amplifiers. The overcurrent latch is set when the current information exceeds the voltage at the ILIM pin. The outputs are immediately disabled, the VR_RDY and DRVON pins are pulled low, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high.
Overvoltage Protection and Power Good Monitor
An undervoltage lockout (UVLO) senses the VCC input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft-start.
Overcurrent Shutdown
An output voltage monitor is incorporated. During normal operation, if the voltage at the DIFFOUT pin exceeds 1.5 V, the VR_RDY pin goes low, the DRVON signal remains high, the PWM outputs are set low. The outputs will remain disabled until the VCC voltage is removed and reapplied. During normal operation, if the output voltage falls more than 350 mV below the DAC setting, the VR_RDY pin will be set low until the output rises.
Soft-Start
A programmable overcurrent function is incorporated within the IC. A comparator and latch make up this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels - effectively disabling overcurrent shutdown. The comparator noninverting input is the summed current information from the current sense
- REMOTE SENSE + AMP VS- VS+ DIFFOUT
The NCP5387 incorporates an externally programmable soft-start. The soft-start circuit works by controlling the ramp-up of the DAC voltage during powerup. The initial soft-start pin voltage is 0 V. The soft-start circuitry clamps the DAC input of the Remote Sense Amplifier to the SS pin voltage until the SS pin voltage exceeds the DAC setting minus VID offset. Thereafter, the soft-start pin is pulled to 0 V. There are two possible soft-start modes: AMD and VR11. AMD mode simply ramps Vcore from 0 V directly to the DAC setting at the rate set by the capacitor connected to the SS pin. The VR11 mode ramps Vcore to 1.1 V at the SS capacitor charge rate, pauses at 1.1 V for 170 ms, reads the VID pins to determine the DAC setting, then ramps Vcore to the final DAC setting at the Dynamic VID slew rate of 6.3 mV/ms. Typical AMD and VR11 soft-start sequences are shown in the following graphs.
+ ERROR AMP C1 1 nF COMP
1.3 V
- R1 10 k VFB
Figure 25. DAC Servo Evaluation Circuit
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NCP5387
2.4 2.2 2.0 1.8 VOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 TIME Vcore Voltage SS Pin Voltage VID Setting
Figure 26. Typical AMD Soft-Start Sequence to Vcore = 1.3 V
2.4 2.2 2.0 1.8 VOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 TIME Boot Dwell Time NCP5387 Internal Dynamic VID Rate Limit Vcore Voltage SS Pin Voltage Boot Voltage VID Setting
Figure 27. Typical VR10 & VR11 Soft-Start Sequence to Vcore = 1.3 V
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NCP5387
APPLICATION INFORMATION The NCP5387 is a high performance multiphase controller optimized to meet the Intel VR11 Specifications. The demo board for the NCP5387 is available by request. It is configured as a four phase solution with decoupling designed to provide a 1.0 mW load line under a 100 A step load. A schematic is available upon request from ON Semiconductor. Startup Procedure The demo board comes with a Socket 775 and requires an Intel dynamic load tool (VTT Tool) available through a third party supplier, Cascade Systems. The web page is http://www.cascadesystems.net/. Start by installing the test tool software. It's best to power the test tool from a separate ATX power supply. The test tool should be set to a valid VID code of 0.5 V or above in-order for the controller to start. Consult the VTT help manual for more detailed instructions.
Startup Sequence
16. Start the second ATX supply by turning it on and setting the PSON DIP switch low. The green VID lights should light up to match the VTT tool VID setting. 17. Set the ENABLE DIP switch up to start the NCP5387. 18. Check that the output voltage is about 19 mV below the VID setting. Step Load Testing The VTT tool is used to generate the high di/dt step load. Select the dynamic loading option in the VTT test tool software. Set the desired step load size, frequency, duty, and slew rate. See Figures 28 and 29.
1. Make sure the VTT software is installed. 2. Powerup the PC or Laptop do not start the VTT software. 3. Insert the VTT Test Tool adapter into the socket and lock it down. 4. Inset the socket saver pin field into the bottom of the VTT test tool. 5. Carefully line up the tool with the socket in the board and press tool into the board. 6. Connect the scope probe, or DMM to the voltage sense lines on the test tool. When using a scope probe it is best to isolate the scope from the AC ground. Make the ground connection on the scope probe as short as possible. 7. Connect the first ATX supply to the VTT tool. 8. Powerup the first ATX supply to the VTT tool. 9. Start the VTT tool software in VR11 mode with the current limit set to 150 A. 10. Using the VTT tool software, select a VID code that is 0.5 V or above. 11. Connect the second ATX supply to the demo board. 12. Set the VID DIP switches. All the VID switches should be up or open. 13. Set the ENABLE DIP switch down or closed. 14. Set the VR10 DIP switch up or open. 15. Set the VID_SEL switch up or open.
Figure 28. Typical Step Load Response
Figure 29. Typical Load Release Event
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NCP5387
Dynamic VID Testing The VTT tool provides for VID stepping based on the Intel Requirements. Select the Dynamic VID option. Before enabling the test set the lowest VID to 0.5 V or greater and set the highest VID to a value that is greater than the lowest VID selection, then enable the test. See Figures 30 through 32. Design Methodology
Decoupling the VCC Pin on the IC
An RC input filter is required as shown in the VCC pin to minimize supply noise on the IC. The resistor should be sized such that it does not generate a large voltage drop between the 5 V supply and the IC.
Understanding Soft-Start
The controller supports two different startup routines. An AMD ramp to the initial VID code, or a VR11 Ramp to the 1.1 V VID code, with a pause to capture the VID code then resume ramping to target value based on an internal slew rate limit. See Figures 33 and 34. The controller is designed to regulate to the voltage on the SS pin until it reaches the internal DAC voltage. The soft-start cap sets the initial ramp rate using a typical 5.0 mA current. The typical value to use for the soft-start cap (SS) is 0.01 mF. This results in a ramp time to 1.1 V of 2.2 ms based on equation 1.
dt Css ^ iss ss dvss 1.1 * V + dvss and i + 5 * mA ss 2.2 * ms dtss Css + 0.01 * mF
(eq. 1)
Figure 30. 1.6 to 0.5 Dynamic VID Response
Figure 31. Dynamic VID Settling Time Rising Figure 33. VR11 Startup
Figure 32. Dynamic VID Settling Time Falling
Figure 34. AMD Startup
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NCP5387
Programming the Current Limit and the Oscillator Frequency The demo board is set for an operating frequency of approximately 330 kHz. The ROSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual RLIM1 and RLIM2 values for the divider. The series resistors RLIM1 and RLIM2 sink current from the ILIM pin to ground. This current is internally mirrored into a capacitor to create an oscillator. The period is
proportional to the resistance and frequency is inversely proportional to the total resistance. The total resistance may be estimated by equation 2. This equation is valid for the individual phase frequency in both three and four phase mode.
RTOTAL ^ 24686 30.5 * kW ^ 24686 Fsw-1.1549
(eq. 2)
330-1.1549
Figure 35.
The current limit function is based on the total sensed current of all phases multiplied by a gain of 6. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum current limit Calculate the current limit voltage:
VILIMIT ^ 6 * IMIN_OCP * DCRTmax )
based on the expected average maximum temperature of the inductor windings.
DCRTmax + DCR25C * (eq. 3) (1 ) 0.00393 (T max -25))
DCRTmax * Vout * Vin-Vout * (N-1) * Vout L L 2 * Vin * Fsw
(eq. 4)
Solve for the individual resistors:
V * RTOTAL RLIM2 + ILIMIT 2*V Final Equation for the Current Limit Threshold ILIMIT(Tinductor) ^
2 * V * RLIM2 RLIM1)RLIM2
(eq. 5)
RLIM1 + RTOTAL-RLIM2
(eq. 6)
6 * (DCR25C * (1 ) 0.00393(TInductor-25)))
*
Vout * Vin-Vout * (N-1) * Vout 2 * Vin * Fsw L L
(eq. 7)
The inductors on the demo board have a DCR at 25C of 0.75 mW. Selecting the closest available values of 16.9 kW for RLIM1 and 13.7 kW for RLIM2 yield a nominal operating frequency of 330 kHz and an approximate current limit of 152 A at 100C. The total sensed current can be observed as a scaled voltage at the VDRP pin added to a positive, no-load offset of approximately 1.3 V.
Inductor Selection When using inductor current sensing it is recommended that the inductor does not saturate by more than 10% at maximum load. The inductor also must not go into hard saturation before current limit trips. The demo board includes a four phase output filter using the T50-8 core from Micrometals with 4turns and a DCR target of 0.75 mW @ 25C. Smaller DCR values can be used, however, current sharing accuracy and droop accuracy decrease as DCR decreases. Use the excel spreadsheet for regulation accuracy calculations for a specific value of DCR.
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NCP5387
Inductor Current Sense Compensation The NCP5387 uses the inductor current sensing method. This method uses an RC filter to cancel out the inductance of the inductor and recover the voltage that is the result of
Rsense(T) +
the current flowing through the inductor's DCR. This is done by matching the RC time constant of the current sense filter to the L/DCR time constant. The first cut approach is to use a 0.1 mF capacitor for C and then solve for R.
(eq. 8)
L 0.1 * mF * DCR25C * (1 ) 0.00393 * (T-25))
was 4.42 kW which matches the equation for Rsense at approximately 50C. Because the inductor value is a function of load and inductor temperature final selection of R is best done experimentally on the bench by monitoring the Vdroop pin and performing a step load test on the actual solution. Simple Average PSPICE Model A simple state average model shown in Figure 37 can be used to determine a stable solution and provide insight into the control system.
Figure 36.
The demo board inductor measured 350 nH and 0.75 mW at room temp. The actual value used for Rsense
E1
+ + --
E 0 GAIN = 6
- + - +
VRamp_min 1.3 V
12 0
1
L
2
DCR (0.85e-3/4)
1
LBRD
2
RBRD 0.75 m CCer (22e-6*18) 1Aac ESRCer 0Adc (1.5e-3/18) 2 ESLCer (1.5e-9/18) 1 0
I1 = 10 I2 = 110 TD = 10u TR = 50n TF = 50n PW = 40u PER = 80u
(250e-9/4)
- +
Vin 12 Voff 0 4 RDRP 5.11 k CH 22 p RF 4.3 k CF CFB1 1.5 n 680 p Unity Gain BW = 15 MHz R6 1k C3 10.6 n 0 RFB RFB1 100
100 p CBulk (560e-6*10) ESRBulk (7e-3/10) 2 ESLBulk (3.5e-9/10) 1
+ -
+ -
I2
1E3
- +
Voff
1k
+ - +
1.3 Voffset
Vout
+ -
VDAC 1.25 V 0
-
0
Figure 37.
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NCP5387
A complex switching model is available by request which includes a more detailed board parasitic for this demo board. Compensation and Output Filter Design The values shown on the demo board are a good place to start for any similar output filter solution. The dynamic performance can then be adjusted by swapping out various individual components. If the required output filter and switching frequency are significantly different, it's best to use the available PSPICE models to design the compensation and output filter from scratch. The design target for this demo board was 1.0 mW out to 2.0 MHz. The phase switching frequency is currently set to 330 kHz. It can easily be seen that the board impedance of 0.75 mW between the load and the bulk capacitance has a large effect on the output filter. In this case the ten 560 mF bulk capacitors have an ESR of 7.0 mW. Thus the bulk ESR plus the board impedance is 0.7 mW + 0.75 mW or 1.45 mW. The actual output filter impedance does not drop to 1.0 mW until the ceramic breaks in at over 375 kHz. The controller must provide some loop gain slightly less than one out to a frequency in excess 300 kHz. At frequencies below where the bulk capacitance ESR breaks with the bulk capacitance, the DC-DC converter must have sufficiently high gain to control the output impedance completely. Standard Type-3 compensation works well with the NCP5387. RFB1 should be kept above 50 W to ensure compensator stability. The goal is to compensate the system such that the resulting gain generates constant output impedance from DC up to the frequency where the ceramic takes over holding the impedance below 1.0 mW. See the example of the locations of the poles and zeros that were set to optimize the model above.
Zout Open Loop Zout Closed Loop Open Loop Gain with Current loop Closed
80 60 40 20 0
Voltage Loop Compensation Gain
1/(2*PI*CFB1*(RFB1+RFB)) 1/(2*PI*CF*RF)
1/(2*PI*RF*CH) Error Amp Open Loop Gain
RF/RFB1 RF/RFB 1/(2*PI*(RBRD+ESRBulk)*CBulk)
dB
-20 -40 -60 -80
1/(2*PI*SQRT(ESL_Cer*CCer)) 1mOhm 1/(2*PI*CCer*(RBRD+ESRBulk))
-100 100
1000
10000
100000
1000000
10000000
Frequency
Figure 38.
By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter.
1 1 + 2p * CF * RF 2p * (RBRD ) ESRBulk) * CBulk 1 1 + 2p * CFBI * (RFBI ) RFB) 2p * CCer * (RBRD ) ESRBulk)
(eq. 9)
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NCP5387
RFB should be set to provide optimal thermal compensation in conjunction with thermistor RT2, RISO1 and RISO2. With RFB set to 1.0 kW, RFB1 is usually set to 100 W for maximum phase boost, and the value of RF is typically set to 4.0 kW. Droop Injection and Thermal Compensation The VDRP signal is generated by summing the sensed output currents for each phase and applying a gain of approximately six. VDRP is externally summed into the feedback network by the resistor RDRP. This introduces an The system can be thermally compensated to cancel this effect to a great degree by adding an NTC (negative temperature coefficient resistor) in parallel with RFB to reduce the droop gain as the temperature increases. The NTC device is nonlinear. Putting a resistor in series with the offset which is proportional to the output current thereby forcing a controlled, resistive output impedance. RRDP determines the target output impedance by the basic equation:
Vout + Zout + RFB * DCR * 6 RDRP Iout RDRP + RFB * DCR * 6 Zout
(eq. 10)
The value of the inductor's DCR varies with temperature according to the following equation 11:
(eq. 11)
DCR(T) + DCR25C * (1 ) 0.00393(T-25))
NTC helps make the device appear more linear with temperature. The series resistor is split and inserted on both sides of the NTC to reduce noise injection into the feedback loop. The recommended total value for RISO1 plus RISO2 is approximately 1.0 kW.
The output impedance varies with inductor temperature by the equation:
Zout(T) + RFB * DCR25C * (1 ) 0.00393(T-25)) * 6 Rdroop
(eq. 12)
By including the NTC RT2 and the series isolation resistors the new equation becomes:
Zout(T) +
RFB * (RISO1)RT2(T))RISO2) RFB)RISO1)RT2(T))RISO2
* DCR25C * (1 ) 0.00393(T-25)) * 6 Rdroop
(eq. 13)
The typical equation of a NTC is based on a curve fit equation 14.
RT2(T) + RT225C * e b 1 *1 298 273 ) T
(eq. 14)
The demo board is populated with a 10 kW NTC with a Beta of 4300. Figure 39 shows the uncompensated and compensated output impedance versus temperature.
VRHOT and VRFAN The NCP5387 provides two threshold sensitive comparators for thermal monitoring. The circuit consists of two comparators that compare the voltage on the NTC pin to an internal resistor divider connected to VREF. By powering the external temperature sense divider with VREF the tolerance of the VREF voltage is canceled out. The data sheet specifications for the thresholds are shown as ratios with respect to VREF. The following equations can be used to find the temperature trip points.
RT1(T) + RT125C * e b RatioNTC(T) : 1 *1 298 273 ) T
(eq. 15)
RNTC2 ) RT1(T) RNTC1 ) RNTC2 ) RT1(T)
(eq. 16)
Figure 39. Uncompensated and Compensated Output Impedance vs. Temperature
The demo board contains a 68 K NTC for RT1 with a Beta of 4750. RNTC1 is populated with 15 kW and RNTC2 is populated with a zero ohm resistor. Figure 40 is a plot of equation 16. The horizontal, trip threshold voltages intersect the RatioNTC curve at the respective activation and deactivation temperature.
ON Semiconductor provides an excel spreadsheet to help with the selection of the NTC. The actual selection of the NTC will be effected by the location of the output inductor with respect to the NTC and airflow, and should be verified with an actual system thermal solution.
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NCP5387
DIFFOUT. If the DIFFOUT signal reaches 180 mV above the nominal 1.3 V offset the OVP will trip. The DIFFOUT signal is the difference between the output voltage and the DAC voltage (minus 19 mV if in VR10 or VR11 modes) plus the 1.3 V internal offset. This results in the OVP tracking the DAC voltage even during a dynamic change in the VID setting during operation. Gate Driver and MOSFET Selection ON Semiconductor provides the NCP3418B as a companion gate driver IC. The NCP3418B driver is optimized to work with a range of MOSFETs commonly used in CPU applications. The NCP3418B provides special functionality and is required for the high performance dynamic VID operation of the part. Contact your local ON Semiconductor applications engineer for MOSFET recommendations. Board Stack-Up The demo board follows the recommended Intel Stack-up and copper thickness as shown.
Figure 40.
OVP The overvoltage protection threshold is not adjustable. OVP protection is enabled as soon as soft-start begins and is disabled when the part is disabled. When OVP is tripped, the controller commands all four gate drivers to enable their low side MOSFETs, and VR_RDY transitions low. In order to recover from an OVP condition, VCC must fall below the UVLO threshold. See the state diagram for further details. The OVP circuit monitors the output of
Figure 41.
Board Layout A complete Allegro ATX and BTX demo board layout file and schematics are available by request at www.onsemi.com and can be viewed using the Allegro Free Physical Viewer 15.x from the Cadence website http://www.cadence.com/.
Close attention should be paid to the routing of the sense traces and control lines that propagate away from the controller IC. Routing should follow the demo board example. For further information or layout review contact ON Semiconductor.
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NCP5387
PACKAGE DIMENSIONS
QFN40, 6x6, 0.5P CASE 488AR-01 ISSUE A
D
PIN ONE LOCATION
AB
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30mm FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 4.00 4.20 6.00 BSC 4.00 4.20 0.50 BSC 0.30 0.50 0.20 ---
2X
0.15 C
2X
0.15 C 0.10 C
40X
0.08 C
L
40X 10 EXPOSED PAD 11
40X b 0.10 C A B
0.05 C
The product described herein (NCP5387), may be covered by one or more of the following U.S. patents: 7,057,381. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EEE EEE EEE
TOP VIEW (A3) SIDE VIEW A1 D2
20 21 1 40 31 30
A
DIM A A1 A3 b D D2 E E2 e L K
C K
40X
SEATING PLANE
SOLDERING FOOTPRINT*
6.30 4.20
40X
0.65 E2 1
4.20 6.30
36X
e BOTTOM VIEW
40X
0.30
36X
0.50 PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP5387/D

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